Field of the Invention
The present invention relates to an image processing apparatus, a method of controlling the same, a non-transitory computer readable storage medium, and a data processing apparatus.
Description of the Related Art
Reconfigurable circuits such as PLDs (Programmable Logic Devices) and FPGAs (Field Programmable Gate Arrays) for which an internal logical circuit configuration is modifiable are well known. In general, PLDs, FPGAs, or the like, are realized by switching functions of the internal logical block by writing logical circuit configuration information stored in a non-volatile memory such as a ROM upon activation to a configuration memory, which is an internal volatile memory. Also, because information within the configuration memory is cleared upon a power supply disconnection, it is necessary for reconfiguration to be performed by writing the logical circuit configuration information into the configuration memory once again upon power supply activation. An approach of performing a configuration of a hardware resource only once in this way is called “static reconfiguration”. Meanwhile, circuits in which it is possible to modify a logical circuit configuration in operation have been developed, and the approach of modifying a logical circuit in operation is called “dynamic reconfiguration”.
Also, in FPGAs, there are those for which it is possible to rewrite a specific region rather than the whole chip, and this kind of rewriting is called “partial reconfiguration”. In particular, performing a partial reconfiguration in a state in which other in operation circuits are not stopped is called “dynamic partial reconfiguration”. In the dynamic partial reconfiguration, by rewriting only a portion of the configuration memory region rather than rewriting the whole configuration memory upon the reconfiguration, it becomes possible to realize a partial reconfiguration of a logical block within the FPGA. By using this kind of dynamic partial reconfiguration technique, it becomes possible to implement a plurality of circuits in one region by switching, and thereby the function that is realized in a logical block in which multiplexing of hardware resources is performed can be modified. As a consequence, it becomes possible to flexibly realize various functions in accordance with the intended uses with less hardware resources while maintaining high computational capabilities with the hardware.
However the logical circuit configuration information, while it is possible to modify the circuit configuration in operation, the time required for modification (rewriting) of the circuit configuration is long, and the time is proportional to the size of the logical circuit configuration information written to the configuration memory. For this reason, conventionally, techniques for reducing the circuit configuration rewrite time have been proposed. As a conventional technique for reducing a rewrite time there is an approach in which, in pipeline architecture processing, reconfiguration on a reconfigurable circuit is performed in order from a leading portion circuit in the pipeline, and activation is performed in order in which the portion circuits are reconfigured (for example, refer to Japanese Patent Laid-Open No. 2011-186981). With this, it is possible to increase data processing speeds more than in an approach of activating having collectively reconfigured reconfigurable circuits simultaneously on a reconfigurable circuit. Also, an approach of holding a plurality of circuits in order to realize predetermined functions and selecting from these in accordance with an operational state is disclosed (for example, refer to Japanese Patent Laid-Open No. 2007-179358).
Meanwhile, an image processing apparatus such as an MFP (Multi Function Peripheral) is capable of selecting a plurality of processes (a color copy job, a monochrome copy job, a print job, a SEND job, or the like) in accordance with a request from a user. Image processing in accordance with these processes is realized by hardware or by software. In general, a logical circuit comprised in hardware is comprised of processing circuits and parameter holding circuits in order to increase versatility, and by modifying parameter coefficients set in the parameter holding circuit, operation and processing details that are necessary in accordance with intended use are realized. Also, it is often the case that setting of parameter coefficients is performed by a CPU.
According to the approach shown in Japanese Patent Laid-Open No. 2011-186981, an order of reconfiguration is controlled in accordance with an order of an image processing unit of a pipeline architecture. However, in a case where a system using a dynamic partial reconfiguration technique for an image processing unit is configured in an image processing apparatus, it is necessary to perform parameter settings after rewriting the circuit configuration of the image processing unit. For this reason, there is a problem in that in addition to the partial reconfiguration time each time the processing is switched, it takes time to set the parameters.
Also, for the approach shown in Japanese Patent Laid-Open No. 2007-179358, there is a problem in that for reconfiguration of a selected logical circuit, in a case where the logical circuit is of a large scale, or in a case where there are many logical circuits that are reconfigured, it takes a long time to perform the reconfiguration.
The present invention, in view of these kinds of problems, makes a start of subsequent processing be earlier when, in an image processing apparatus capable of dynamic partial reconfiguration, processing is switched by modifying parameters.